Archive for November, 2008

This is a follow up to comments on my post AMS assertions… a violation of “the 10 commandments”?

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I think that defining an interface between Verilog-AMS and SV is exactly what is needed. But, instead of doing that, the Accellera committee is trying to define a new “merged” language that can translate analog signal properties into the digital property syntax of SV. This effort fails to understand that what may be an interesting exercise academically does not necessarily equate to the best (or even a viable) solution for the real world.

• More importantly, are we losing sight of “What is the problem that we are trying to solve”?

There are two simple facts that frame this problem.

1. SV only understands boolean values for property checks. That is not going to change.
2. Analog instrumentation is required to perform property checks of an analog circuit or signal. That is not going to change either.

So how should analog meet digital here? If you try to (syntactically) put analog instrumentation in the digital checker it’s pointless, because the execution still must be performed by an analog engine. (Hence all the examples with “special functions”).

In a real-world solution, it makes much more sense to utilize whatever instrumentation fits in the analog engine to test analog properties, rather than obscure that reality in a new language that must be parsed and elaborated for execution in the analog engine anyway.

We can easily communicate boolean values from analog property checkers to SV through a co-simulation interface. A rough implementation of that has already been demonstrated by IIT Kharagpur in their research project “Instrumenting AMS Assertion Verification on Commercial Platforms”.

My proposal is this: create an “AMSproperty” command to complement the current digital “property” functions in SV. Consider this…

• Just as Verilog-AMS supports analysis-dependent functions: analysis (analysis_list)
• Similarly, we could have analysis-dependent assertions: AMSproperty (property type);

The property types would match those in a taxonomy of analog properties. I firmly believe that my taxonomy is a more viable starting point than where this activity sits today, but I would be more than thrilled to see one that represents a consensus of a cross-functional industry committee.

In an integration of analog engines (SPICE, FastSPICE, whatever… with or without Verilog-AMS) with SV, as in the IIT example, parsing of a netlist with an AMSproperty would immediately invoke functions that the analog engine understands. No new language required!

Furthermore, this solution would enable complete coverage of all the property types in the analog taxonomy, which the current SV-constrained discussion does not address. EDA vendors could then build interfaces to whatever analog tool best fits with the properties being checked, and not be limited to time-domain simulation.

Let’s develop a solution that fits the problem, rather than the other way around!

-Mike

The World is Analog

AMS assertions

System Verilog

Verilog-AMS

Accellera

Now… before any religious zealots come after me, “the 10 commandments” that I refer to are in my friend Karen Bartleson’s list of Commandments for Effective Standards. If you have been reading here in recent months, you know that I have been participating in Accellera discussions on the topic of AMS assertions. After the last two meetings, I have grown more concerned that this activity is committing transgressions of Karen’s 3.1th commandment: “Know when to start“. I might modify that slightly to say “know WHERE to start“.

Karen captured the issue well when she wrote “There is a proper time to start a standardization effort for a technology (or format, API, database, …). Before standardizing, it has to have reached a certain level of maturity.”

The problem as I see it is that there is no existing tool, and neither are there any agreed upon best practices, for the realization of Assertion-Based Verification of AMS designs (AMS-ABV). Yes, as I have written here before, there have been some research activities in this area. There are also some who are actively employing existing Verilog-AMS capabilities to implement AMS-ABV. And yes, I am pretty sure that we all agree there is a critical need for improving the productivity of AMS verification by adopting automated checking techniques like ABV. I wouldn’t be here (virtually) if there wasn’t. But advocating a solution (i.e. a merger of SystemVerilog with Verilog-AMS), before reaching agreement on the problem to be solved, seems to be a sign of “premature standardization“ – in my opinon.

I have not been entirely alone on making this point. Another participant in the Nov-4th Accelllera committee meeting asked if we should define requirements before we define syntax. I attempted to define requirements in my Taxonomy of analog properties. This is a classic example of the problems that can arise when “analog meets digital“. Language standardization efforts, by their very nature, are not likely to attract active involvement from those of us who would say “I’m an analog“. We just aren’t very interested in designing languages. Where we focus on transistors and circuits, the digital types focus on syntax; regular expressions, special functions and my favorite… syntactic sugar. Special functions are required because SystemVerilog is a digital verification language (doh!). More than once, in the last two meetings, someone has pointed out that Verilog-AMS can already do what the language definers are trying to re-invent. Why force a round peg into a square hole? Is this going to make AMS verification any easier?

I have nothing against language definition per se, if that’s what you’re into. But, at some point, reality has to settle in and the language needs to be implemented in a simulator(s). I found this quote from Karen’s 3rd commandment to be especially apropos:

“There are dozens of EDA standards sitting on the shelf unused. (Remember VHDL Waves?) Resources consumed by these standards could certainly have been better spent. Working on a standard that isn’t going anywhere is a senseless waste.”

Several examples of AMS SystemVerilog assertion prototypes are now being discussed in the Accellera meetings. You can go to the Accellera Verilog Analog Mixed-Signal Group repository to download the documents. If you have used Verilog-A/AMS, you probably have learned that one of the best practices is minimal use of analog event statements like @cross. Well folks… forcing the “round peg” of analog (continuous time) properties into the “square hole” of digital (discrete time) checkers requires creating and monitoring a ton of analog events! The problem expands many times over when you play tolerances into the equation, as you will see in the example prototypes. We are in danger of defining a language that is completely impractical to implement and apply. As it currently stands, the examples could only be implemented in a post-simulation waveform calculator… not exactly a novel concept.

Finally – even with the most brilliant definition of how to do AMS-ABV, it would be meaningless if no EDA vendor signs up to create an implementation. This Accellera activity is very different than the Verilog-AMS effort that I participated in ten years ago. At that time Verilog-A had already been introduced, in Cadence’s Spectre-a as well as in Meta-Software’s HSPICE. The leaders of this project are a semiconductor vendor (Freescale) and a research institute (Verimag). There are a few participants from Synopsys and Mentor, with little or no participation from Cadence. Clearly, to achieve a meaningful consensus on advancing AMS verification with assertion techniques more participation is needed. The discussions take place every other Tuesday morning, moving to 10AM central U.S. time on Dec-2. I believe that you can mailto:verilog-ams@eda.org if you would like to join the discussion.

-Mike

p.s.

You may notice some slight changes to the Analog Insights page. First – you will note that my introduction in the “About” right sidebar has changed. I think that an update was long overdue, but this also will now reflect the fact that I am no longer employed by Synopsys. However, Analog Insights lives on, and Synopsys has encouraged me to continue posting here. I am very gratified at the tremendous growth in subscribers over the last year, so I am glad that I won’t be losing that audience.

At the same time, I now have an opportunity to revive my personal blog; The World is Analog. You will note that link is now on my blogroll in the left sidebar as well. I had started blogging on my own site a few months before the launch of Analog Insights, but decided to shut it down for reasons that you can read about there. The World is Analog will reflect my broader interests in topics beyond AMS verification. I hope that you come by to check it out, and subscribe there as well.

analog
AMS verification
System Verilog
Accellera
Verilog-AMS
assertion-based verification

Hello Everyone,

Are you attending ICCAD in San Jose this week? Even if you’re not, but you are in Silicon Valley Wednesday afternoon Nov-12, here is your opportunity to see what EDA bloggers look like in real life. (Here’s a secret… we wonder what you look like all the time). And best of all… it’s FREE and you don’t need to be registered for ICCAD to attend.

Ed Lee (of Lee Public Relations) and Sean Murphy (of SKMurphy, Inc.) have organized a EDA Bloggers’ “Birds-of-a-Feather” meeting, to be held at 4:00 PM in the Fir Ballroom at the San Jose DoubeTree Hotel. If you are thinking of starting your own blog, this will be a great place to start by meeting a group of the EDA industry’s most experienced bloggers. The event will feature a mix of bloggers from EDA companies, journalists, users and EDA consultants. I will be joining this group of my fellow bloggers for a 3-minute “Lightning Talk” on the topic of how to develop an audience for your blog.

Confirmed presenters:

• Karen Bartleson http://synopsysoc.org/thestandardsgame/
• John Blyler http://www.chipdesignmag.com/blyler/
• John Busco http://jab-semi.blogspot.com/
• Grant Martin http://www.chipdesignmag.com/martins/
• Rick Munden http://blog.freemodelfoundry.com/
• Sean Murphy http://www.skmurphy.com/blog/
• Warren Savage http://www.design-reuse.com/blogs/oncores

For more details, see Sean’s blog or the ICCAD website.

-Mike
blogging
ICCAD
EDA