Archive for February, 2008

The second paper from the Analog/Mixed-Signal Verification session at DVCon-08 was presented by Jeff McNeal of Synopsys’ Intellectual Property Solutions Group:

7.2 Methodology for Modeling Analog Circuits Using Behavioral Verilog

Chris Jones, Jeff McNeal – Synopsys, Inc.

The work that was described in this presentation also addressed the problem of verifying the interaction between digital and analog circuits in mixed-signal designs (as in the 1^st paper: Thomas J. Sheffler Functional Verification in the Presence of Linear Analog Circuits), but went further by describing a comprehensive methodology to integrate synthesized and custom digital blocks as well as the interaction between analog modules that communicate across different levels of a chip’s hierarchy.

The verification methodology described here can itself be thought of as hierarchical, since it employs progressive refinement from higher level behavioral models all the way to transistor-level circuit models (for analog blocks) as a design proceeds from the top-level architectural definition through implementation and signoff. The Verilog PLI is also used extensively in this verification flow, with analog behavior represented by a small library of primitive functions that convert (to or from) real-number variables that are assigned to represent voltage or current values on digital wires. Here is an example from the author’s paper at last year’s DVCon (ref: C. S. Jones, J. McNeal, and R. Segelken, “Sending Analog Values Along Digital Wires”, DVCon 2007) of a PLI function to convert a real-number variable to a value on an output net:

$ana_voltage_source(wire_out, real_val)

In the earlier paper by Sheffler, the objectives for the analog behavior to be modeled were simpler – representing the conversion of a digital control word to an analog voltage. There is a requirement to model higher level analog/mixed-signal functions in the methodology described in this paper, so rather than solve for DC voltages and currents Verilog behavioral models are used to directly calculate analog values, such as in this example of a DAC (also from the same author’s paper at DVCon 2007):

The paper provides a comprehensive set of rules for applying this verification methodology, which I won’t go into here, but I highly recommend getting a copy if you are interested in more details.

My thoughts:

Once again; this paper provides another alternative for modeling the type of mixed-signal behavior that Verilog-AMS was developed for. To be fair; the Verilog-AMS language provides the capability to model much more elaborate analog and mixed-signal behavior, but that analog behavior must be calculated by a SPICE engine. Developing Verilog-AMS models is a difficult skill to master, and it is easy to create a model that is functionally correct but is bad in terms of how it affects simulation performance.

It is also apparent that for purposes of functional verification, at least in these examples of D/a designs, the event-driven approach controlled by a digital simulator is sufficient. It is also clear that the simulation performance during verification is of utmost importance when Analog meets Digital. Of course, much verification time is still consumed outside of this flow, by the analog block designers running SPICE and Fast-SPICE.

One obvious problem with any hierarchical verification methodology is how to check the behavioral models against the actual circuitry. In many cases the models are checked manually, and the assumption is that the analog designers have sufficiently verified their transistor-level blocks. I like that the methodology presented in this paper is more robust, because co-simulation of Verilog with Fast-SPICE is used as the final sign-off verification. The authors point out that judicious use of co-simulation is a requirement for catching subtle model mismatches, and is considered a necessity to increase confidence before tapeout.

Have you used SPICE or Fast-SPICE co-simulation with Verilog or VHDL?  What about Verilog or VHDL AMS extensions?  Are AMS behavioral modeling languages useful, or do they just slow down digital simulations?

I’m looking forward to your comments.

-Mike
DVCon AMS Verification Verilog Co-simulation Behavioral Modeling

Hi All,

DVCon, which describes itself as “the premier conference for functional design and verification of digital electronic systems“, was held in San Jose on February 19-21. Though the conference emphasizes digital systems, some of the challenges of verifying the increasing amount of mixed-signal content in SOCs were addressed in the Analog/Mixed-Signal Verification session on Thursday morning.

Here are my notes from the first paper, in what turned out to be a very interesting session at DVCon last week. I will follow with my review of the other two papers in that session.

7.1: Functional Verification in the Presence of Linear Analog Circuits

The first presentation was from Thomas J. Sheffler of Rambus, Inc. Thomas’s presentation described a solution for verifying the behavior of analog circuits that are parametrically controlled by digital logic as part of a “big-D/little-a” system. The example used was a PHY output driver that is tuned through programmable current DACs to minimize reflections and interference on a high-speed serial data link. Digital control modulates the voltage value that is transmitted based on the calibrated, weighted sum of the bit stream to reduce inter-symbol interference.

The system verification challenge is to confirm that the proper bit voltage is implemented for a given control word value, and to check for errors such as swapped or inverted control bit logic. In this case the analog values that must be measured are actually piece-wise constant, simplifying the problem by requiring only DC measurements. I am seeing many examples like this however, where the need is for a mechanism to read-back analog values for verification in a digital environment. The 2^nd paper in this session also addressed this in a different way.

Functional verification was complicated by the segmented DAC architecture which employed a combination of binary-weighted current sources for the LSBs, along with equally-weighted thermometer-coded current sources for the MSBs. This type of DAC architecture creates the possibility for an incorrect control code to produce the “correct” output voltage, since each of the MSBs has the same weight.

The novel solution offered here was to build a Verilog PLI library of models for linear circuit elements that are parameterized by passing real values (i.e. the analog quantities – resistance, DC current, etc.) during simulation. The Verilog Procedural Interface (VPI) enables C-language function calls to the models, and Verilog register values can then be used to control each parameterized element. By interconnecting instances of the linear model building blocks, the complete functionality of a DAC-controlled PHY can be emulated. A voltage probe is also included in the model library, to read the electrical value of the output result that is to be tested and compare it to the expect value.

My thoughts:

This paper reinforces the need for an efficient way to model digitally-controlled analog circuits in D/a designs, so that mixed-signal blocks can be incorporated easily in digital verification methodologies. It was interesting to me that the authors dismissed Verilog-AMS as a solution because of concerns for computational overhead in an analog solver. These are precisely the type of problems that the analog extensions to Verilog were intended to address. In the case of dynamic simulation, it is true that performance can be dominated by the nonlinear differential equations that must be solved for the analog portion of a mixed-signal circuit.

However, by abstracting analog behavior to linear piecewise-constant models the problem is converted to simple DC nodal analysis – and there is no longer any need for solving differential equations. This should eliminate the concern for computational overhead of a SPICE simulator in transient mode. Simple co-simulation through VPI or a commercial AMS simulator that integrates Verilog with a SPICE or Fast-SPICE engine, such as in Synopsys’ Discovery-AMS, would suffice. Co-simulation of SPICE with Verilog functions as an event-driven interface, where the Verilog simulator makes calls to the SPICE solver – just as was done here with a specialized nodal analysis algorithm. It would be interesting to compare performance to see which is faster.

But, perhaps a full-blown SPICE or Fast-SPICE engine would be overkill. Let me ask you, my readers…

Are there many AMS verification problems that would require only a DC SPICE capability to be linked to a Verilog or VHDL simulator?

What are your thoughts?

-Mike
Fast-SPICE

AMS Verification

Verilog

DVCon

Hi All,

Now how’s that for a subject line? Sounds pretty theoretical doesn’t it?

Well, don’t worry, this is not going to be some academic treatise on numerical methods or matrix algebra. My objective is simply to clear up any confusion that may exist regarding how Fast-SPICE accelerates regular SPICE simulation.

Not all Fast-SPICE simulators are hierarchical. As far as I know, hierarchical simulation was an innovation that was introduced by Nassda in what is now Synopsys’ HSIM (HS = hierarchical storage). The illustration below shows how it works. Hierarchical storage just takes advantage of the fact that most circuits are hierarchical, consisting of multiple instances of subcircuits, so that memory storage can be reduced by only storing a subcircuit once. This does not affect accuracy at all, but it does speedup up simulation by creating a smaller image of the circuit in memory. Obviously, memory circuits can take the greatest advantage of this, but circuit designers know that subcircuit reuse and hierarchy is by no means unique to memory designs. Similarly, Fast-SPICE simulators that exploit this technique are not just for memories, as one of the speakers at the recent DesignCon claimed. Exploiting hierarchy is one of those obvious things that, once you see it, you wonder why all simulators don’t work that way. Much more efficient!

Hierarchical storage is sometimes confused with the other Fast-SPICE innovation introduced by HSIM, the IM=isomorphic matching. Isomorphism refers to the identification of structurally and ELECTRICALLY identical structures during simulation. This technique is used during simulation, whereas hierarchy is used during the initial netlist read-in.

When a simulator like HSIM uses isomophism, identical instances throughout the hierarchy are evaluated to determine if their port currents and voltages match to within a (user-controllable) tolerance. If they don’t match, each instance is solved individually. If they do match, then why waste the time? This could result in a speed-accuracy tradeoff if the tolerances are too large, or the isomorphism is only transient, but it can dramatically speed up many simulations with no significant loss of accuracy as well.

In post-layout designers quite often have one big flat netlist, and one might think that this means that hierarchical Fast-SPICE no longer applies. Not true! It is very rare that every transistor or subcircuit instance is entirely unique, even after parasitic extraction and back-annotation. A simulator like HSIM, along with the HSIM^plus post-layout technology, is capable of re-constructing hierarchy even from a flat parasitic extraction and back-annotation in order to maintain the performance benefits of hierarchy and isomorphic matching. This provides a unique double benefit, where Fast-SPICE may be both FASTER and MORE ACCURATE than SPICE. (Another truism that belies the myth of “analog Fast-SPICE“).

With Hierarchical Back-Annotation, it is possible to simulate a circuit that was just too large or too slow to even think about simulating in a conventional SPICE simulator that lacks hierarchy and isomorphism. As a result, a designer would have to compromise with only a pre-layout simulation or by piecing together a set of smaller simulations, hoping that the results were accurate. Hierarchical Fast-SPICE can handle the post-layout parasitics much better, and as a result more accurate and faster post-layout verification can be achieved.

-Mike

FastSPICE isomorphism hierarchical simulation HSIM

HSIM

Hello Everyone,

Recently I have spoken to a few readers of my blog who asked me if there was a way that they could be automatically informed when a new article is posted. Many of you may be new to blogs, which are generally broadcast via the internet by a mechanism called an RSS (Really Simple Syndication) feed. The nice thing about RSS feeds is that once you setup an RSS reader in your browser, the new content automatically gets pushed to you. All you need to do is check your browser for updates. In this post, I’ll show you how to use the most popular RSS readers to subscribe to my blog.
If you look at the upper left corner on this blog’s web page http://synopsysoc.org/analoginsights/ you will see a set of buttons that you can use to subscribe to our RSS feed. My favorite way to read blogs is through My Yahoo! Pages, so I’ll start by showing an example of that. One of my favorite features of My Yahoo! is that they let you create as many tabbed pages as you want with your customized content. I have a My Yahoo! page just for my AMS and EDA-related RSS feeds. All you need is a Yahoo account.

The screen shot above shows what happens if you are logged into your Yahoo account, and you click on this button:

Once you select “Keep It”, you can return to you’re My Yahoo! Page at any time, and you will see the headline for new posts, and the indication of how long ago they were posted.

Many of you may have Google accounts for email, or be users of the Google homepage. If you select this button: Google presents you with two options for reading my blog:

If you select “Add to Google homepage”, it is very similar to My Yahoo!, except they don’t show you any information on the age of the posts:

You can also select “Add to Google Reader”, which creates a separate page where you can directly read any blog, or click to go to the blog site if you choose. The list view in the Google reader shows the date of posts, and highlights those that are unread in bold. The “Expanded view” lets you read the blog directly, while the right arrow next to each post goes to the blog site.

Finally, here is one more easy way to keep track of blog updates if you are a Firefox user. Firefox has a feature called “Live Bookmarks”. If you look at this blog in Firefox, you will notice the RSS icon alongside the URL:

If you click on that icon, Firefox responds by asking if you want to save a bookmark:

Now you can see a list of the blog posts simply by looking at your bookmarks.How do you read my blog? Do you go directly to the blog site? Let me know if I can help make it easier for you to read and stay up to date.

-Mike

v:* {behavior:url(#default#VML);} o:* {behavior:url(#default#VML);} w:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} blog readers RSS My Yahoo! Google Live Bookmarks Firefox

Hi All,

I’m still digesting the information overload from ISSCC, but I wanted to share a few highlights and observations. I will follow up with more details in upcoming posts.

1. The program committee did a great job with juxtaposing industry insider-outsider presentations in the Plenary session. H.K. Lim of Samsung presented a vision of very large displays (80 inches) as the center of the digital home, followed brilliantly by Bill Buxton of Microsoft literally taking a different angle with his presentation on surface computing. The 2nd sequence of presenters was Mike Muller of ARM presenting on embedded processing, followed again with a fresh, more visionary outsider perspective by Jeff Hawkins (inventor of the Palm PDA), on Why Can’t A Computer Be More Like A Brain? Jeff’s new company, Numenta, is doing some very interesting work in this area.

2. The (under-reconstruction) San Francisco Marriott (c’mon.. who needs a bar in the lobby just taking up space during the day, when you already have a bar on the top floor with such a great view?) should consider themselves very fortunate that there was not an earthquake or other incident during the conference. With an estimated 3500 people in what is basically the basement, the traffic flow that now forces everyone through a narrow corridor in order to get back to the surface-level lobby is idiotic, dangerous, and probably illegal. There was a major human traffic jam the 1st day at the lunch break, with everyone completely stalled on stair cases and escalators waiting to squeeze through to exit.

3. As expected, the numerous sessions on new accomplishments in AMS design disproves the notion put forth in the press recently that AMS design must go off chip in the new nanometer processes. Texas Instruments, ST Micro, NXP and others showed great working examples of advanced AMS designs all the way down to the 45nm process node.

4. Interesting that the 2 Data Converter sessions were the most popular of any that I attended. My take is that the growing “digital revolution” creates an even greater need for the functions that go in and out to the real Analog World.

5. TI reversed what has been accepted as an inevitable increase in leakage power at smaller process nodes, through very sophisticated on-chip power management. In their 45nm DSP presentation, they showed how new techniques such as back-biasing, actually LOWERED the leakage power compared to their 65nm design. It was also interesting to see how much circuit design goes into power management for other digital designs.

6. The integration of radios on an AMS SoC goes on to higher levels of performance and sophistication for WiMax, 802.11, UWB, mobile video, etc. It is mandatory to achieve this integration in order to achieve cost targets for developing consumer market segments.

More later.

-Mike
SoC ISSCC AMS design leakage power Marriott 45nm