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Analog Insights: Analog/Mixed-Signal Design and Verification Blog
|Analog Insights: Analog/Mixed-Signal Design and Verification Blog|
Welcome to Analog Insights! Our goal is to have an innovative, informative and interactive blog about AMS, from purely analog to mixed signal and RF. AMS is a challenging and fast paced place, so let’s have fun with it and mix it up! I hope you enjoy this blog.
Interestingly, I have been wanting to be an engineer since a very young age. After getting a degree in Doctoral studies in EE, I worked at Motorola, within their advanced process and research center as a Device and Spice characterization engineer for 5 years. I then moved to the EDA industry and have been happily working there for 12 years in the AMS domain. I have multiple technical publications under my belt and am currently the chair(wo)man for DesignCon Analog and Mixed Signal track. Why AMS? Because AMS is a fascinating environment with multiples aspects and challenges that evolve extremely quickly, where you keep redefining solutions and pushing the limits. Now about me, I could say I am French, that I like wine and eat cheese but that would be a little cliché, wouldn’t it? Let’s just say that I am active, that I like to be challenged in life and in sports and that I have a passion for swimming.
Posted by Hélène Thibiéroz on February 27th, 2015
DVCON 2015 is just around the corner so I wanted to inform you on several events we are having there to showcase VCS AMS:
- VCS AMS at Synopsys booth #101 :
We will demo VCS AMS in areas appealing to digital verification engineers: Easy transition from digital to mixed-signal, increased performance using Save and Restore, AMS testbench or how to extend UVM to analog, UPF extended to analog and Debugging AMS using Verdi
- Synopsys luncheon: Prashanth Gurunath from Xilinx will talk about VCS AMS usage in his presentation “Addressing Unique Verification Challenges of Mixed-signal with VCS AMS”
- We will have a specific mixed-signal technical Session on UPF: Mixed-Signal Verification of UPF Based Designs; Andrew S. Milne, Damian Roberts – Synopsys, Inc.
You can find more information at the following link:
Looking forward to seeing you there !
Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on January 15th, 2015
I just wanted to remind our dear Synopsys HSPICE users (and other AMS aficionados..) about our yearly HSPICE SIG event. This event has grown other the years and present each year topics related to circuit simulation challenges. Because HSPICE combines transistor-level accuracy with comprehensive signal integrity analysis, and is the golden reference for IBI and IBIS-AMI modeling, the SIG presentations this year will focus on signal and power integrity analysis of multi-gigabit serial links.
DATE: January 28, 2015
TIME: 6:00 p.m.-9:00 p.m.
LOCATION: Santa Clara Marriott Hotel
2700 Mission College Boulevard
Santa Clara, CA 95054
To register to our event, you can use the link listed below:
In addition to prividing a great dinner and technical presentations by industry leaders and Synopsys R&D, we will also host a cocktail hour where our HSPICE Integrator Program partners will exhibit their circuit simulation solutions.
We are looking forward to meeting you there.
Posted in AMS Circuits, AMS EDA tools, analog design, Signal Integrity | No Comments »
Posted by Hélène Thibiéroz on January 13th, 2015
Happy new year everyone,
The Synopsys AMS Special Interest Group (SIG) is an active community for all Synopsys analog/mixed-signal users and design engineers who want to stay connected with the latest developments in the field of analog/mixed-signal circuit simulation, cell characterization, and custom design.
We are hosting again our AMS SIG event in Bangalore, India on January 21, 2015 at the Park Plaza Hotel . At this event, Analog Devices, ARM, STMicroelectronics and Xilinx panelists will share their insights about using Synopsys’ AMS verification solution for some of today’s most challenging designs, ranging from mixed-signal verification for various design architectures to complex reliability challenges for full-custom IP. The panelists will also discuss future verification needs, as well as the methodology and tool requirements to support modern AMS verification. In addition, Synopsys will present the latest challenges in AMS verification and innovations and new technology features to address those challenges. Lunch will follow to allow attendees to network with our panelists.
To register to this unique event, please go to:
I hope you would appreciate our event, as our goal was to focus on getting some of our most advanced customers present their analog mixed-signal challenges and solutions.
As usual, your comments are more than welcome
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on October 8th, 2014
VCS AMS is doing really well. After a successful webinar with ST and ARM and the release of a white paper, we are continuing our momentum with a tutorial at DVCON Europe on Tuesday, October 14th:
This highly technical tutorial will presents how the VCS AMS mixed-signal verification solution provides superior performance and flexibility. It was developed around best-in-class methodologies to extend proven digital verification techniques into mixed-signal designs. VCS AMS encompasses, but is not restricted to, capabilities for time efficient simulations using “Save and Restore” technology, aligned with the SV1800 industry standard syntax for “SystemVerilog nettype” constructs, represented as a holistic methodology within AMS Testbench that is underpinned by extremely successful UVM library.
The breadth and depth of usage of the individual portions within the solution are explained by real user case studies: extensive usage of VCS AMS Save and Restore for boosting productivity by STMicroelectronics and performance-driven VCS AMS behavioral modeling flow by Micronas.
So yes, you will miss Octoberfest but you get to attend an amazing webinar
In addition, if you want to access our previous webinar and review VCS AMS white paper “Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS”, I have listed the links below.
VCS AMS webinar
VCS AMS white paper
As usual, your feedback is more than welcome.
Posted in Uncategorized | No Comments »
Posted by Hélène Thibiéroz on September 2nd, 2014
I hope you all had a relaxing labor day weekend. To start fall successfully :), we are releasing a joint webinar on VCS AMS with STMicroelectronics and ARM as guest speakers on Wednesday, September 3rd, at 10am PST.
You can register using the following link:
This webinar includes:
- An introduction to the VCS AMS mixed-signal verification solution and key capabilities for coverage-driven AMS testbench development, low-power mixed-signal verification, and regression throughput
- Highlights of how STMicroelectronics is successfully using VCS AMS for both verifying mixed-signal designs using techniques such as assertions and scoreboarding as well as accelerating regression test throughput with the Save and Restore capability
- A description of how ARM is able to use the advanced verification techniques and productivity features of VCS AMS for its validation methodology of physical IP (I/O interface).
This webinar is part of a series on VCS AMS, you can access previous webinars using the following links:
Hope to see you there!
Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on July 11th, 2014
We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST. The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.
Our panelists shared their experiences and insights using VCS AMS, our mixed-signal verification solution that incorporates VCS functional verification and CustomSim™ FastSPICE simulator.
We had a packed room and heard many positive comments from the attendees.
Now, if you did not get a chance to attend this amazing event , the videos of all above presentations are now available at the following link:
Below are the titles of the presentations and highlights of the event:
Micronas speaker highlighted how they use mixed-signal verification to ensure “Zero PPM quality” for their customers in automotive applications. They emphasized the need for high performance simulation with SPICE-level accuracy and touted VCS AMS using a reusable testbench strategy for multiple behavioral vs. SPICE netlist configurations as a key methodology for ensuring first-pass silicon success.
Infineon shared the verification challenges they have faced for ARM-based SoCs targeted at a broad array of applications including Automotive, Security, and Energy. They highlighted how the high performance and flexibility of VCS AMS coupled with post-layout support for parasitic/timing back-annotation with CustomSim have helped them to verify the power-up sequence in their complex mixed-signal designs and prevent possible design failures.
AMD described how they have deployed a reusable UVM testbench environment for mixed-signal verification of their complex SerDes PHYs. The speaker shared their successful delivery of IP designs for 28nm and 20nm technologies using VCS AMS, including multicore CustomSim FastSPICE engine, in their regression farm.
ST highlighted how they drive the verification of their Analog/Mixed-Signal systems using VCS AMS and a digital testbench. They showed a detailed comparison of VCS AMS versus competition and emphasized VCS AMS as including the “best FastSPICE engine” and offering the best “Speed and Accuracy” for mixed-signal verification.
So as you can see, a very succesful event so we hope to see you next year !
As usual, any comments or suggestions are more than welcome. Feel free to contact me anytime.
Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on May 28th, 2014
DAC is here and we are ready!
You may have seen at SNUG that we announced VCS AMS, Synopsys advanced mixed-signal verification initiative to enable faster regression testing of Mixed-Signal SoCs.
We therefore decided to focus our DAC AMS luncheon technical event on VCS AMS. As a result, we have a very impressive panel of industry experts composed of AMD, Infineon, Micronas and STMicroelectronics. They will share their experiences and methodologies and highlight VCS AMS as the best mixed-signal verification tool available for today and tomorrow SoC designs (not my words, they did tell us without any torture or bribes :)).
Our speakers are (in chronological order):
Micronas : “Verification of Analog-on-Top Mixed-Signal ICs”
Infineon: “Power Aware Mixed-signal SoC Verification using VCS AMS”
AMD: “Exhaustive Verification OF Mixed-signal Designs using VCS AMS”
ST Microelectronics : “VCS AMS in STMicroelectronics”
Those presentations will portray Synopsys mixed-signal verification solution for performance, flexibility, advanced verification and low power capability, as shown by the table below.
Because we wanted to offer a depth and breadth of understanding of verification challenges and related solutions, this AMS lunch-on should be extremely valuable to anyone involved with advanced mixed-signal verification and/or looking at extending their digital methodologies to mixed-signal.
To register to this event you don’t want to miss – of course you don’t – you can use the link listed below:
Hope to see you there!
Posted in AMS Circuits, AMS EDA tools, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on March 27th, 2014
You may have seen Synopsys recent announcement during SNUG:
In a few words, Synopsys is announcing an initiative to accelerate regression testing of mixed-signal SoCs. As part of the initiative, Synopsys is rolling out a SystemVerilog-based methodology, AMS Testbench, and the new VCS® AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim™ FastSPICE simulator.
You are going to ask me, what is VCS AMS?
VCS AMS is Synopsys’ advanced mixed-signal verification solution, incorporating VCS functional verification and the CustomSim™ FastSPICE simulator, to deliver advanced functional and low-power verification technologies combined with industry-best performance and capacity for faster mixed-signal SoC regression testing.
What are the capabilities and benefits of VCS AMS?
VCS AMS key capabilities and benefits are:
- Industry-best performance and capacity from tight integration of VCS functional verification and CustomSim FastSPICE simulator to accelerate regression testing of mixed-signal SoCs with transistor-level accuracy
- AMS Testbench enables design teams to rapidly extend their existing UVM-based digital verification environments for mixed-signal SoC regression testing
- Mixed-signal low-power verification with VCS native low power (NLP) technology, supporting UPF, for mixed-signal designs quickly identifies power management design errors during simulation
- Support for complex design architectures mixing SPICE, Verilog, VHDL, SystemVerilog, Verilog-A and Verilog-AMS enables quicker development of mixed-signal verification environment
- Save and restore capability enables faster regression testing throughput by resuming simulation from a previously-saved initialization state
By leveraging industry-best mixed-signal verification performance and capacity, a proven SystemVerilog-based verification methodology extended for mixed signal and advanced functional and low power verification technologies, VCS AMS provides not only a faster solution of mixed-signal SoC verification but also a superior environment to rapidly deploy constrained-random testbench in a mixed-signal regression environment.
More information can be found at:
If you would like to receive even more information on VCS AMS , please contact me anytime.
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on February 27th, 2014
For Mixed-Signal afficionados or wannabes attending DVCON, I will be moderating next Monday a panel session on Mixed-signal verification (not on French wine making yet, sorry ) . This event is sponsored by Accellera and more information can be found at:
As SoC designs evolve from a “chip design” to a “chip assembly” methodology, new constraints and verification needs are emerging, raising the necessity for an intelligent “mixed-signal verification”. I was fortunate to get experts in this area from various backgrounds and representing various industries to share their insights and debate about the future of mixed-signal verification and emerging trends.
Our panelists are:
Scott Little – Intel Corp.
Scott Morrison – Texas Instruments, Inc.
Neyaz Khan – Maxim Integrated
Martin O’Leary – Qualcomm, Inc.
Several topics would be discussed, from new behavioral modeling standards to Digital verification techniques applied to mixed-signal and Debugging/regression mixed-signal environment.
We certainly hope to see you there !
More information is also available at:
Posted in AMS EDA tools, Mixed Signal/Cosimulation, verification | No Comments »
Posted by Hélène Thibiéroz on January 23rd, 2014
You may be tired of hearing only about Mixed-signal verification, so why don’t we switch to signal Integrity? . Looking at the recent announcements at CES and Intel’s expected release of server solutions using DDR4 memory later this year, I wanted to further explore this topic. We had a little time ago a very successful webinar that showed in more details DDR capabilities that SI users have and are currently adopting using a combined Synopsys- Zuken flow. Because of our customer testimonies and their enthusiasm on those capabilities, I therefore asked the owners (Griff, Hany) to demo this flow at DesignCon at the ChipHead theatre (see link below) and to talk to us a little more. Our Synopsys WaveView expert Manu V. Pillai is joining the discussion as well to provide more insights on WaveView, which is used by this flow.
Griff Derryberry is an application engineer at Zuken. He focuses on helping customers realize high-speed designs using Zuken’s enterprise PCB solutions.
Manu Velayudhan Pillai has been working with Synopsys Spice simulation tools for over 7 years and currently responsible for Analog/Mixed-signal environment and waveform tool WaveView. He is involved in developing DDR3/DDR4 specific measurements and has been working closely with large companies demonstrating the unique capabilities of WaveWiew for DDR capabilities.
Q1 – Griff, can you educate us on the main DDR challenges you are seeing from both a timing and physical design aspects?
Griff: The main challenges that DDR poses from both timing and physical design aspects includes the need for creating serpentine traces so that setup and hold timing is achieved across a set of nets. This serpentining of traces consumes available real estate, making achieving timing closure more difficult to attain.
Q2- Can you please provide us more insights on the combined Zuken – Synopsys flow you will demo at DesignCon ?
Griff: The Zuken environment provides the design capture, constraint management, and physical realization tools to place and route the DDR system. The Zuken toolset creates the HSPICE netlist containing lossy impedances based on the trace widths and board stackup. HSPICE simulates the result and the timing is validated in Custom WaveView. We will show all aspects of this flow at DesignCon.
Q3- This capability relies heavily on Synopsys Waveform viewer WaveView . Which unique features does WaveView offer for signal integrity?
Manu: Custom WaveView has a powerful EYE diagram measurement tool, which performs basic measurements like height, width, aperture, skew, masks for both transient and STATEYE outputs. The DDR3 specific measurements like derate based setup/hold, tVAC, ringback violations, in Custom WaveView not only generates the reports but also pinpoint the violations in transient signal for further debugging. The built-in Jitter vs Time tool measures pulse-width, periodic, cycle-to-cycle jitter for SI applications. All the measurements can be automated using ACE-TCL scripts and run it in batch-mode hence saving verification time. Overall, a very intuitive and powerful solution.
Q4. There are number of companies showing off their DDR4 memory and Intel is expected to bring out server solutions that use DDR4 memory later this year, are you looking into DDR4 capabilities as well? On a more general scope, which challenges and new features do you see moving forward?
Manu: JEDEC has changed the timing and voltage measurements of DDR4 specifications. The derate based setup/hold measurements in DDR3 are not going to be used in DDR4 and new specification contains Mask based approach which includes deterministic & random jitters. In addition to this DDR4 designs will have a varying Vcent value compared to DDR3 designs.
The upcoming release of Custom WaveView will address the challenges of DDR4 timing and voltage measurements. Waveview measures the Vcent_DQ value, and calculates the eye shifts needed for each DQ pins to get maximum aperture along with other measurements like VdIVW_Total, TdIVW_Total, and SRIN_diVW.
Thanks Griff and Manu for this introduction. In the event you are further interested in Synopsys DDR capabilities, feel free to contact me anytime. I have listed below the references to our different events.
Link to DesignCon event:
Link to Synopsys-Zuken webinar
Link to Synopsys WaveView datasheet:
Posted in AMS Circuits, analog, analog design, Signal Integrity, SPICE, Uncategorized | No Comments »
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