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Analog Insights: Analog/Mixed-Signal Design and Verification Blog

VCS AMS – Synopsys advanced mixed-signal verification solution to accelerate regression testing of mixed-signal SoCs

Posted by Hélène Thibiéroz on March 27th, 2014

 You may have seen Synopsys recent announcement during SNUG:

http://news.synopsys.com/2014-03-25-Synopsys-Unveils-Advanced-Mixed-Signal-Verification-Initiative-to-Accelerate-Regression-Testing-of-Mixed-Signal-SoCs

In a few words, Synopsys is announcing an initiative to accelerate regression testing of mixed-signal SoCs. As part of the initiative, Synopsys is rolling out a SystemVerilog-based methodology, AMS Testbench, and the new VCS® AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim™ FastSPICE simulator.

You are going to ask me, what is VCS AMS?

VCS AMS is Synopsys’ advanced mixed-signal verification solution, incorporating VCS functional verification and the CustomSim™ FastSPICE simulator, to deliver advanced functional and low-power verification technologies combined with industry-best performance and capacity for faster mixed-signal SoC regression testing.

VCS AMS

 

What are the capabilities and benefits of VCS AMS?

VCS AMS key capabilities and benefits are:

  • Industry-best performance and capacity from tight integration of VCS functional verification and CustomSim FastSPICE simulator to accelerate regression testing of mixed-signal SoCs with transistor-level accuracy
  • AMS Testbench enables design teams to rapidly extend their existing UVM-based digital verification environments for mixed-signal SoC regression testing
  • Mixed-signal low-power verification with VCS native low power (NLP) technology, supporting UPF, for mixed-signal designs quickly identifies power management design errors during simulation
  • Support for complex design architectures mixing SPICE, Verilog, VHDL, SystemVerilog, Verilog-A and Verilog-AMS enables quicker development of mixed-signal verification environment
  •  Save and restore capability enables faster regression testing throughput by resuming simulation from a previously-saved initialization state

 

By leveraging industry-best mixed-signal verification performance and capacity, a proven SystemVerilog-based verification methodology extended for mixed signal and advanced functional and low power verification technologies, VCS AMS provides not only a faster solution of mixed-signal SoC verification but also a superior environment to rapidly deploy constrained-random testbench in a mixed-signal regression environment.          

More information can be found at:

http://www.synopsys.com/Tools/Verification/AMSVerification/Pages/vcs-ams-ds.aspx

If you would like to receive even more information on VCS AMS :) , please contact me anytime.

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Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »

DVCON 2014 – Panel on Mixed Signal Verification: what’s next ?

Posted by Hélène Thibiéroz on February 27th, 2014

For Mixed-Signal afficionados or wannabes attending DVCON, I will be moderating next Monday a panel session on Mixed-signal verification (not on French wine making yet, sorry :) ) . This event is sponsored by Accellera and more information can be found at:

http://dvcon.org/content/event-details?id=163-250

As SoC designs evolve from a “chip design” to a “chip assembly” methodology, new constraints and verification needs are emerging, raising the necessity for an intelligent “mixed-signal verification”. I was fortunate to get experts in this area from various backgrounds and representing various industries to share their insights and debate about the future of mixed-signal verification and emerging trends.

 

Our panelists are:

Scott Little – Intel Corp.

Scott Morrison – Texas Instruments, Inc.

Neyaz Khan – Maxim Integrated

Martin O’Leary – Qualcomm, Inc.

Several topics would be discussed, from new behavioral modeling standards to Digital verification techniques applied to mixed-signal and Debugging/regression mixed-signal environment.

We certainly hope to see you there !

More information is also available at:

https://www.semiwiki.com/forum/content/3118-update-ams-verification-dvcon.html

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Posted in AMS EDA tools, Mixed Signal/Cosimulation, verification | No Comments »

Synopsys/Zuken at DesignCon- Unique DDR capabilities using WaveView and HSPICE

Posted by Hélène Thibiéroz on January 23rd, 2014

You may be tired of hearing only about Mixed-signal verification, so why don’t we switch to signal Integrity? :) . Looking at the recent announcements at CES and Intel’s expected release of server solutions using DDR4 memory later this year, I wanted to further explore this topic. We had a little time ago a very successful webinar that showed in more details DDR capabilities that SI users have and are currently adopting using a combined Synopsys- Zuken flow. Because of our customer testimonies and their enthusiasm on those capabilities, I therefore asked the owners (Griff, Hany) to demo this flow at DesignCon at the ChipHead theatre (see link below) and to talk to us a little more. Our Synopsys WaveView expert Manu V. Pillai is joining the discussion as well to provide more insights on WaveView, which is used by this flow.

Griff Derryberry is an application engineer at Zuken. He focuses on helping customers realize high-speed designs using Zuken’s enterprise PCB solutions.

Manu Velayudhan Pillai has been working with Synopsys Spice simulation tools for over 7 years and currently responsible for Analog/Mixed-signal environment and waveform tool WaveView. He is involved in developing DDR3/DDR4 specific measurements and has been working closely with large companies demonstrating the unique capabilities of WaveWiew for DDR capabilities.  

Q1 – Griff, can you educate us on the main DDR challenges you are seeing from both a timing and physical design aspects?

Griff:  The main challenges that DDR poses from both timing and physical design aspects includes the need for creating serpentine traces so that setup and hold timing is achieved across a set of nets.  This serpentining of traces consumes available real estate, making achieving timing closure more difficult to attain.

Q2- Can you please provide us more insights on the combined Zuken – Synopsys flow you will demo at DesignCon ?

Griff:  The Zuken environment provides the design capture, constraint management, and physical realization tools to place and route the DDR system.  The Zuken toolset creates the HSPICE netlist containing lossy impedances based on the trace widths and board stackup.  HSPICE simulates the result and the timing is validated in Custom WaveView.  We will show all aspects of this flow at DesignCon.

 

Q3- This capability relies heavily on Synopsys Waveform viewer WaveView . Which unique features does WaveView offer for signal integrity?

Manu: Custom WaveView has a powerful EYE diagram measurement tool, which performs basic measurements like height, width, aperture, skew, masks for both transient and STATEYE outputs. The DDR3 specific measurements like derate based setup/hold,  tVAC, ringback violations, in Custom WaveView not only generates the reports but also pinpoint the violations in transient signal for further debugging. The built-in Jitter vs Time tool measures pulse-width, periodic, cycle-to-cycle jitter for SI applications. All the measurements can be automated using ACE-TCL scripts and run it in batch-mode hence saving verification time. Overall, a very intuitive and powerful solution.

 

Q4. There are number of companies showing off their DDR4 memory and Intel is expected to bring out server solutions that use DDR4 memory later this year, are you looking into DDR4 capabilities as well? On a more general scope, which challenges and new features do you see moving forward?  

Manu: JEDEC has changed the timing and voltage measurements of DDR4 specifications. The derate based setup/hold measurements in DDR3 are not going to be used in DDR4 and new specification contains Mask based approach which includes deterministic & random jitters. In addition to this DDR4 designs will have a varying Vcent value compared to DDR3 designs.

The upcoming release of Custom WaveView will address the challenges of DDR4 timing and voltage measurements. Waveview measures the Vcent_DQ value, and calculates the eye shifts needed for each DQ pins to get maximum aperture along with other measurements like VdIVW_Total, TdIVW_Total, and SRIN_diVW.

Thanks Griff and Manu for this introduction. In the event you are further interested in Synopsys DDR capabilities, feel free to contact me anytime. I have listed below the references to our different events.

Link to DesignCon event:

http://www.designcon.com/santaclara/schedule-builder/session-id/827664

Link to Synopsys-Zuken webinar

https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=723324&sessionid=1&key=80FFE92F0C3CFB226A5C42468C86AF22

Link to Synopsys WaveView datasheet:

http://www.synopsys.com/Tools/Verification/AMSVerification/DesignAnalysis/Pages/CustomWaveView.aspx

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Posted in AMS Circuits, analog, analog design, Signal Integrity, SPICE, Uncategorized | No Comments »

HSPICE SIG, DesignCon, Busy month for Synopsys AMS

Posted by Hélène Thibiéroz on January 17th, 2014

 As DesignCon conference approaches and as the chairman of the AMS track, I would like to inform you on a few technical events happening there. In addition to our AMS track, we have added several events:

  •  An interactive presentation by Zuken and Synopsys on a unique and innovative solution to characterize signal integrity analysis of ddr3 high-speed memory interface. As DDR is becoming more and more a hot topic (as seen at CES and with the recent Intel expected move to DDR4 memory), I am expecting this presentation to be appealing to a lot of signal integrity users.

http://www.designcon.com/santaclara/schedule-builder/session-id/827664

I will be further describing this approach next week with the presenters.

  •   A unique PLL tutorial “Modeling PLLs for AMS Design and Verification” that would give you insights from both an “intra-PLL” modeling aspect (i.e. modeling interactions inside the PLL) and “inter-PLL” modeling one (modeling complete PLLs for interaction in the greater system). I worked on PLL modeling for several years and I think this tutorial will be really educational.

http://www.designcon.com/santaclara/schedule-builder/session-id/826658

 

In addition to that, Synopsys will be hosting its annual HSPICE SIG event. This year, the SIG presentations will focus on signal and power integrity analysis of multi-gigabit serial links. HSPICE combines transistor-level accuracy with comprehensive signal integrity analysis, and is the golden reference for IBIS and IBIS-AMI modeling. In addition, HSPICE is integrated with major electromagnetic solvers and SI environments. So it complements extremely well DesignCon areas of interest and we hope to see you there.

http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/hspice-sig2014.aspx

So as you can clearly see, busy month for AMS :)

Hope to see you at some of those events. As usual, if you have any technical questions on any of those topics, feel free contact me.

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Posted in AMS EDA tools, analog design, Device Modeling, Mixed Signal/Cosimulation, Signal Integrity | No Comments »

MTV 2013 AMS Panel – The Future of Mixed-Signal Verification: from Simple Simulation to Full Regression?

Posted by Hélène Thibiéroz on January 9th, 2014

Happy new year ! I chaired and organized a panel on Mixed Signal Verification at MTV 2013 conference last December and wanted to share some of my insights with you.

In just a decade, the landscape of mixed-signal design has drastically changed. While API simulations between a digital and analog solver have evolved into a more complex mixed-signal environment that includes multiple languages and technologies, those changes are still not enough to address today’s challenging design needs.

While the future of mixed-signal verification is unclear due to the diversity of use models and needs, you can still see some emerging trends, particularly for digitally-driven mixed-signal system-on-chip (SoC) design teams.  I therefore wanted to explore and highlight in a panel those emerging trends and asked technical experts from various backgrounds to join me in this discussion at MTV 2013 conference:

http://mtvcon.org/advance-program/

Several topics were discussed, from new behavioral modeling standards to Digital verification techniques applied to mixed-signal and Debugging/regression mixed-signal environment.

The panel included both professionals from several major design houses (Intel, Freescale) as well as EDA vendors. I have asked one of our speakers, Ron Shebel, to present his views and insights.

Ron received his BSEE from Purdue University in 1989. He joined Motorola/FreeScale Semiconductors from 1989 to 2004 as a Memory Designer specializing in Memory Compiler design and custom SRAM design. He then joined  Synopsys Inc in 2004 and is currently a Senior Staff Application Engineer focusing on Spice-Fastspice and Mixed-Signal Verification.

Question 1 : Hi Ron, you were one of the panel attendees, What was your overall impression and takeaways for this event?

Ron Shebel, Synopsys Inc.

Ron- The event was well received and attended.  As for the panel discussion itself, I think there was a lot of interaction between the panel and the audience.   The main points that came across were that Mixed-Signal Verification is key in the design of SOCs but there are many challenges in regards to debug of these simulations as well as shear thru put of the simulation engines.  This is why higher level modeling is also needed.

Question 2- New Behavioral  Modeling Standards: Various modeling methods (SystemVerilog-AMS, SystemC-AMS) are emerging today to resolve some existing limitations when passing information between analog and digital blocks within a mixed-signal SoC. What were the original motivation and goals behind these language enhancements? What are their current status?

Ron- The basic reason for these new behavioral standards is to allow more modeling options outside of the traditional Spice –Verilog.  There are also some known limitation with some of the existing languages today, creating bottlenecks and need for workarounds while working at the top-level. The validation of complex systems  which includes the verification of IP spice blocks is becoming more of the norm than in the past.  Synopsys is actively working with leading edge customers to implement new standards. One emerging standard is SystemVerilog-AMS, where AMS constructs are being added to SystemVerilog to allow users  to alleviate the bottlenecks that exists with traditional spice simulations.  Another standard that we at Synopsys are embracing is SV-nettype  which make system Verilog much more power in terms of real number modeling. Synopsys is actively working with main SoC customers on this implementation.

Question 3- Digital Verification techniques applied to Mixed Signal: There is a crucial need to port proven digital verification methodologies into mixed-signal SoC design. Industry standard verification methodologies have been enhanced with new analog-focused capabilities to extend for mixed-signal verification.  What are the features and advantages offered by such flows?

Ron- The biggest advantage that I see is the direct re-use of digital testbenches within a  Mixed-Signal environment.  Digital concepts such as coverage, assertions, checkers are enhanced to work in a Mixed-Signal environment. Because we have seen our main SoC customers evolving from a Digital only to a mixed signal domain, Synopsys has implemented for a few years a methodology allowing to extend your Digital methodology to Mixed-Signal.  Synopsys AMS testbench (previously called UVM-AMS) offers assertions, checkers, testbench generators that can be applied to analog entities. We have now several large customers using and looking at this technology.

Synopsys AMS testbench

 

Question 4 -Debugging/Regression environment: A mixed-signal environment has multiple facets, depending on a design team’s use model. Which features should such a debugging and regression management tool include to meet tomorrow verification needs?

Ron- Debug is key to Mixed-Signal Verification.  A mixed-signal GUI that allows not only invoking simulations but also debugging is critical.  Being able to transverse both rtl code and spice netlist as well as point and click features to see the exact states and voltages  is what is needed. Moving forward, there would also be a need to coordinate digital and analog methodologies to ensure maximum coverage and bug detection.  Synopsys by leveraging different tools (Verdi from the digital side and SAE for the analog one) is actively working on implementing specific features to debug specifically for mixed signal designs.

Thanks Ron and thanks to all for reading.  If you have any questions regarding this event or any of Synopsys offerings, feel free to contact me anytime.

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Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »

Optimized Synopsys-MathWorks solution for System-Level Verification

Posted by Hélène Thibiéroz on November 14th, 2013

Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs

With the increasing complexity of those designs, there is a crucial need today for a system-level verification methodology:   verification engineers need to be able to take a system they designed at a higher level of abstraction and verify it against their RTL and mixed-signal flows, allows them to have increased confidence in their design, and identify and fix defects or bugs.

MathWorks and Synopsys have been developing new capabilities to significantly improve productivity in these verification activities, including deployment of models to SystemVerilog to provide a more integrated verification workflow.

As such, I wanted to talk today about this co-joint effort led by Mathworks and Synopsys to provide a unique solution to deliver such methodology. I have asked Arun Mulpur from MathWorks and Rebecca Lipon from Synopsys VG to give us more insights about this solution and its benefits.

Arun Mulpur has been with MathWorks since 2002 and currently manages a team of industry marketing managers that focus on communications, electronics, semiconductors, medical devices and robotics industries. He works with key customers worldwide to discuss their application requirements and workflow gaps, and addressing them in collaboration with key EDA partners.

Rebecca Lipon is currently the Senior Product Marketing Manager for Synopsys Verification products. Rebecca has over a decade of experience in the semiconductor industry with engineering roles at Synopsys, SGI, and ATI. She holds a BS in Electrical Engineering & Computer Science from MIT.

 Helene> Arun, Rebecca: Can you give us some background on this methodology? What were the driving factors of this successful collaboration between Mathworks and Synopsys?

Arun: Engineering teams predominantly use MATLAB, Simulink, and Model-Based Design for their algorithm and behavioral designs. They create executable specifications, golden reference models, and high level algorithmic implementations in MATLAB and Simulink and use them throughout the system design, prototyping, implementation, and verification stages. As a consequence of the above trends, these engineering teams are looking for ways to integrate their MATLAB and Simulink models in with their core digital, analog, and mixed-signal IC design and verification flows which are predominantly based on Synopsys tools and methodologies.

Both Synopsys and MathWorks are hearing from mutual customers about the need to bridge these two worlds and enable more streamlined verification of complex ASIC and SoC designs. We have started working together to develop and provide such capabilities and are happy to announce that initial solutions are available now.

Rebecca:  Simulation remains the mode by which 60% or more of design bugs are found. By providing a tighter integration with high-level algorithmic solutions like MATLAB and Simulink with the VCS verification sign-off flow, customers have increased confidence in the logic they have designed. Model-based design solutions allow architects to fully explore their best design implementation, but without integrating it into the same verification flow used to validate the RTL implementation of the design, significant risk may exist. We are excited to provide a more usable and robust solution for our joint customers to reduce their risk and increase their confidence in their final design implementation. 

Helene> Arun, you have been deeply involved with the development of Synopsys/Mathworks flow, can you give us more technical insights on the two flows we currently support?

Arun:

For Interactive debugging and unit-level testing: if the primary need is for verification of digital algorithms or system components, and a part of the Device Under Test (DUT) or test bench is expressed in VHDL or Verilog, we recommend cosimulation as the first step during initial interactive design and unit testing stages. In this scenario, both MATLAB & Simulink and VCS simulation engines are running simultaneously – either on the same machine or on different servers in a network – and executing different parts of the test bench and the DUT run in their own environment. C/C++ portions can run in either environment depending on how the simulation is configured. This workflow ensures that IP components have been verified according to the golden reference or executable specification.

For production verification and validation: In this scenario, engineers model, simulate, and verify digital or mixed-signal algorithms or system components in Simulink and MATLAB. To integrate these IP components and test benches with other components in VCS, Simulink can export these models as C code with SystemVerilog wrappers. These components can be used in VCS along with other SystemVerilog components or test benches for verification of the complete system design. In this case, when the simulation executes in VCS, Simulink and MATLAB simulation engines are not involved, and all the components run natively and exclusively in VCS.

 

Helene> How do you see this flow evolve moving forward based on how digital and mixed signal verification are evolving? What would be next?

Arun:

To learn more: The cosimulation and System Verilog export capabilities are both available now. Please contact MathWorks if you want to evaluate them or need more information. Additionally, one of the use cases that we are hearing from our mutual customers is the need for analog cosimulation interface between Simulink and Synopsys environments such as HSIM. If this use case is of interest, and you are interested in working together with Synopsys and MathWorks to explore possible solutions within the framework of a pilot project, please contact MathWorks.

Rebecca: We have invested significantly in fast analog-mixed signal cosimulation, native low power simulation, and many other advanced flows including this new cosimulation mode with MATLAB/Simulink in order to address the increasing complexity of our customers’ designs. Enhancements in AMS methodology and language support, as well as increased automation to allow users to cover more complex scenarios as efficiently as possible, get better coverage across mixed-simulation modes, and leverage closer integration with key partners are all areas of focus for us moving forward. We want to minimize customer’s risk, and increase the capacity to verify their complex designs within their time-to-market windows, so we are improving performance, capacity, coverage, automation, debug, and integration.

Thanks Arun and Rebecca for this very interesting discussion. If you want to hear more about this co-joint solution, you can find some details at:

http://www.mathworks.com/products/hdl-verifier/description5.html

Feel free as well to contact me anytime. And as usual, feedback is more than welcome :)

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Posted in AMS EDA tools, digital, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »

DVCON Videolog on “User Experiences at the Forefront of Mixed-Signal Verification” now available

Posted by Hélène Thibiéroz on October 31st, 2013

I know, it’s been a while… )

Well sadly, I have no other excuse than just being busy… Since fall is usually the beginning of hibernation, I have decided to buck this trend and start blogging again, as we are going to have many events and new features to cover for Mixed-Signal Verification in the coming months.

If you are familiar with my blog, you may have read some time ago a summary report on the DVCon tutorial on “User Experiences at the Forefront of Mixed-Signal Design and Verification” (see link below):

http://blogs.synopsys.com/analoginsights/2013/03/07/dvcon-2013-mixed-signal-verification-tutorial-insights-from-our-speakers/

This tutorial was very well attended by digital and AMS engineers due to the versatility and depth of its content.

Well, this is your lucky day—this amazing event is now available online…and at no cost :) ! You can access it on the Accelera website at:

http://www.accellera.org/resources/videos/mixedsignaluser

As usual, feedback is more than welcome…

And lastly, because today is Halloween and I could not resist, I am enclosing a picture of the best Mixed-Signal costume I could find..


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Posted in Uncategorized | No Comments »

DesignCon 2014 AMS verification track – Call for papers open until Aug 5th

Posted by Hélène Thibiéroz on July 25th, 2013

Happy Thursday ! I can’t believe it is already end of July…

Talking about end of July, I wanted to reach to our AMS community regarding DesignCon 2014. As you may (or may not… ) know, I chair the Analog and Mixed-Signal Design and Verification track for DesignCon 2014. Our call for papers is now open and the deadline for proposals is August 5th, 2013. Note that paper proposals need only include a short abstract and summary to be considered by the DesignCon Technical Program Committee. Full paper submissions are not due until November 19th, 2013. Regular papers at DesignCon are presented in 40 minute sessions. However, if you have content that requires a more in-depth treatment, we encourage you to submit an abstract for a Tutorial Session, which can be 3 hours in duration.

Samples topics can be:

Design & verification methodologies

Simulation algorithms and techniques

Mixed-signal behavioral modeling approaches

Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog, SystemC-AMS, etc.

Mixed-domain design and verification solutions

MEMS, electro-optics, mechatronics, etc.

Mixed-domain/mixed-language verification strategies

Analog IP: selection, integration, and modeling

Coverage, metrics, and closure management

Yield analysis, Monte Carlo methods, and optimization approaches

On-chip inductors: design and modeling

RLCK extraction: post-layout flows and strategies

Noise analysis and prediction: substrate, spurious, random

Variability effects and statistical analyses

You can look at the DesignCon Call for Abstracts page for additional information:

http://www.designcon.com/santaclara/call-for-submissions/

Thank you for your future participation at DesignCon! We hope to see you there.

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Posted in AMS Circuits, AMS EDA tools, IEEE Conferences, Uncategorized, verification | No Comments »

DAC 2013 AMS Verification event videolog

Posted by Hélène Thibiéroz on June 27th, 2013

 Well after a couple of busy weeks traveling (and I am sure you really care about knowing this :) ), I finally found some time to blog about our DAC AMS event held in Austin early June. We had a very successful event with some great technical presentations (hey that’s the feedback I received from the crowd..) from Micron, Broadcom, ST-Ericsson E, ARM and ST-Microelectronics. The topics ranged from low power and reliability and mixed signal verification and advanced memory characterization.

 

Related information can be found in my previous post:

http://blogs.synopsys.com/analoginsights/2013/05/22/dac-2013-ams-verification-luncheon-advance-your-mixed-signal-verification-techniques-to-the-next-level/

Since a video is more efficient those days than a lengthy PhD dissertation, I am listing below the link to our event:

http://www.synopsys.com/Tools/Verification/AMSVerification/Pages/dac-2013-ams-verification-luncheon.aspx

Enjoy and, as usual, feedback  is more than welcome !

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Posted in AMS Circuits, AMS EDA tools, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Reliability, SPICE, verification | No Comments »

DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level

Posted by Hélène Thibiéroz on May 22nd, 2013

 

Well DAC 2013 is around the corner, so I guess it is time to blog about it, especially since this is in Austin :)

 And no, I am not going to tell you about the best BBQ joints or sushi places (yes I did say sushi in Texas) since I lived there for almost 15 years, but I’m going to tell you about our DAC AMS lunch event.

 http://www.synopsys.com/Tools/Verification/AMSVerification/Pages/dac-2013-ams-verification-luncheon.aspx

 We wanted this year to present some of the challenges Synopsys customers face to ensure successful AMS design validation for advanced process nodes. Consequently, our topics vary from low power and reliability to mixed-signal verification and memory characterization.

 Our speakers are industry experts coming from various sectors (SoC, Mobile, Memory, SRAM, etc.) so they will present a very exhaustive landscape of those challenges as well as Synopsys latest flows and features to further tune your current AMS methodologies for performance and accuracy. Now, I am listing below companies, titles and abstracts, that would probably convince you more than a long marketing speech :)

 Our speakers are (in chronological order):

 Micron Off-Chip and On-Chip Power Delivery Modeling with HSPICE

 Abstract: Power delivery for a part (be it memory, logic, or otherwise) is of paramount importance, requiring the need to design a Power Delivery Network system which is optimized for the various models of die demand, at the least risk of resonances. Hspice and Finesim are used to characterize the various block models, to spot potential problems and finally to run transient sims to validate AC optimization.

ARMOvercoming Challenges of FinFET Memory IP using FineSim

 Abstract: FinFET process technology offers significant improvements in performance and power efficiency of ARM-based SoCs. Along with these improvements come many challenges in the design, margin analysis and model generation for advanced embedded memory. During this luncheon ARM will discuss some of the key challenges of FinFET memory development and how Synopsys’ FineSim fast SPICE simulator is used to provide full-featured, high-quality ARM Artisan® memory IP for mobile, network storage and server applications.

 STE- Improve IC-level verification coverage by using assertions with CustomSim-VCS multi-thread real number flow

 Abstract: Time and resources to ensure a good coverage for IC-level functional verifications are growing year after year with design complexity. There is, therefore, a need to reduce simulation setup and analysis. Discovery-AMS with VHDL Real Number approach permits to maximize and accelerate verification coverage by creating easily co-simulation setup and taking advantage of FastSPICE multithreading.

Broadcom- Advanced Memory characterization using FineSim for performance and accuracy

Abstract: Broadcom has developed a complex internal flow to create and characterize compiled memories that are used throughout their production chips. This flow highly leverages Synopsys’ flagship simulators FineSimPro and FineSimSpice. The simulators are used to characterize the memory for three distinct needs, timing, power and leakage. BRCM fine tunes FineSim technology to give the required accuracy/performance needed for each area of characterization.

ST : Aging model implementation using MOSRA API flow from HSPICE to CustomSim

 Abstract: An innovative platform of reliability simulation including all front-end wear-out mechanisms is presented. Customized physics-based models of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are implemented in MOSRA. The aging models are developed for HSPICE simulator and extended to FastSPICE CustomSim. Aging simulation with CustomSim is a promising solution enabling the robustness assessment of large circuit and providing both accuracy and speed.

Because we wanted to offer a depth and breadth of understanding of verification challenges and related solutions, this AMS lunch-on should be extremely valuable to anyone involved with advanced AMS verification.

Hope to see you there!

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Posted in AMS Assertions, AMS EDA tools, Mixed Signal/Cosimulation, Reliability, verification | 4 Comments »